1. Field of the Invention
The present invention relates generally to a logic circuit and, more particularly, to an ECL (Emitter Coupled Logic) circuit suitable for a high-speed large scale ECL circuit and Bi-CMOS LSI.
2. Description of the Background Art
An ECL circuit normally belongs to a bipolar integrated circuit and has a characteristic of operating at a frequency as high as 300 MHz or above.
FIG. 13 is a circuit diagram illustrating a construction of a first conventional ECL circuit shown in FIG. 1 of Japanese Patent Laid-Open Publication No.7-142991.
This circuit is a 3-input OR/NOR gate ECL circuit based on a 2-stage construction consisting of a differential logic stage including a current switch and an output emitter follower stage serving as a buffer output.
Three NPN transistors Q101-1, Q101-2, Q101-3 connected in parallel form an arm on one side of the differential logic stage, and, besides, with bases thereof serving as input terminals of the circuit of the differential logic stage, input signals INA, INB, INC are respectively supplied thereto. A reference potential defined an earth potential is supplied to a collector common connecting point via a load resistor R101, and a constant current source ICS is connected to an emitter common connecting point. Further, an arm on the other side of the differential logic stage is constructed of an NPN transistor Q102 a base of which is supplied with a reference potential VBB1. Then, a collector thereof is supplied with the reference potential as the earth potential through a load resistor R102, and an emitter thereof is connected to the constant current source ICS.
In this circuit, if one or more signals among the three input signals INA, INB, INC supplied to the bases of the three NPN transistors Q101-1, Q101-2, Q101-3 is higher than the reference potential VBB1, the relevant NPN transistor is turned ON, whereby the current starts flowing across the load resistor R101. With this inflow of the current, the potential at the emitter common connecting point rises till the NPN transistor Q102 is turned OFF. In this state, no current flows across the load resistor R102. At lest one of the NPN transistors Q101-1, Q101-2, Q101-3 is turned ON, whereas the NPN transistor Q102 is turned OFF. Hence, a collector potential of the left-side arm assumes an "L" level, while a collector potential of the NPN transistor Q102 takes an "H" level. Normally, the emitter follower circuits are connected as output stages respectively to the two arms of the differential logic stage, and a base of an emitter follower NPN transistor is connected to a connecting point between the load resistor R101 or R102 and the collector of the transistor. Accordingly, when the current flows through the input-side arm of the differential logic stage, an output Z of the emitter follower stage of the other-side arm is set at the "H" level, and an output /Z of the emitter follower stage of the input-side arm of the differential logic stage is set at the "L" level.
On the other hand, when all the three input signals INA, INB, INC become lower than the reference potential VBB1, a current ICS of the constant current source ICS flows to the other-side arm of the differential logic stage. Then, the output Z assumes the "L" level, and the output /Z takes the "H" level.
As discussed above, with respect to the logic output Z, OR outputs of the three input signals INA, INB, INC are obtained.
FIG. 14 is a circuit diagram showing a construction of a second conventional ECL circuit shown in Japanese Patent Laid-Open Publication No.7-142991.
This circuit is referred to as an active pull-down ECL circuit or an APD (Active Pull-Down) circuit that can be constructed to permit a flow of large transient current when switching but to consume a small steady-state current when remaining static.
The differential logic stage is constructed of two pieces of NPN transistors Q101, Q102, and an input signal IN is supplied to a base of the NPN transistor Q101 Then, the reference potential defined as the ground potential is supplied to a collector of the NPN transistor Q101 via the resistor R101. The constant current source ICS is connected to an emitter common connecting point of the NPN transistors Q101, Q102, and a power supply VEE is connected to the other side of the constant current source ICS. A connecting node A between the resistor R101 and the collector of the NPN transistor Q101, is connected to a base of a charge bipolar transistor QU. The reference potential as the ground potential is supplied to the collector of the charge bipolar transistor QU, and an emitter thereof is connected to a collector of the NPN transistor Q102 via the resistor R102. A base of the NPN transistor Q102 is supplied with the reference potential VBB1. A connecting node between the emitter of the transistor QU and the resistor R102 is connected to a collector of a discharge NPN bipolar transistor QD, and serves as an output terminal OUT. The base of the discharge NPN bipolar transistor QD is connected to a connecting node B between the resistor R102 and the collector of the NPN transistor Q102, and the emitter of the discharge NPN bipolar transistor QD is supplied with a reference potential VREG.
In this circuit, when the potential at the connecting node point A falls in a state where a large capacitance is connected to the output terminal OUT, the charge bipolar transistor QU momentarily cuts off. At this time, the potential at the base point B of the transistor QD rises, and the emitted of the transistor QD is supplied with the reference potential VREG. Therefore, the transistor QD is strongly switched ON. That is, an inter base-emitter voltage increases, and a large collector current flows. Accordingly, electric charges accumulated in the load capacitance are abruptly discharged via the transistor QD. The circuit is constructed so that a fall propagation delay time is thereby reduced.
Further, Japanese Patent Laid-Open Publication No.7-58617 discloses an ECL circuit constructed such that the reference potential VREG in the ECL circuit in FIG. 14 serves as a supply reference potential VEE, wherein an operating principle thereof is the same as that of the ECL circuit in FIG. 14.
The problems existing in the ECL circuits shown in FIGS. 13 and 14 are as follows.
In the first ECL circuit in FIG. 13, when the potential of the other-side arm rises to the "H" level from the "L" level upon a turn-OFF of the NPN transistor Q101, the output Z is driven by an emitter follower transistor Q104, and hence a switch-over is carried out at a high speed. When the potential of the other-side arm falls down to the "L" level from the "H" level upon a turn-ON of the NPN transistor Q102, however, the fall propagation delay time thereof largely depends on a static current flowing across the emitter follower output stage, and a switching operation is slow in the ECL circuit on a long-wired chip. Then, the problem is that the electric power is more consumed as the operation is more speeded up.
On the other hand, in the second ECL circuit in FIG. 14, there exists the following problem.
FIG. 15 is a circuit diagram showing a construction of the second ECL circuit (APD circuit) in FIG. 14 when actually used. As illustrated in FIG. 15, when actually requiring the second ECL circuit (APD circuit) in FIG. 14, a constant potential generating circuit for generating a proper constant potential VREG is needed. Besides, another APD circuit is also normally connected to a VREG line supplied with the constant potential VREG. It is assumed that a plurality of APD circuits in FIG. 15 include the APD circuit defined as the second ECL circuit in FIG. 14, and it is also considered that outputs of all the APD circuits simultaneously fall in a state where the plurality of APD circuits are connected to the constant potential generating circuit for generating the constant potential VREG.
When the output of all the APD circuits simultaneously fall, the discharge NPN bipolar transistor QD is strongly switched ON, and the electric charges accumulated in the load capacitance flow into the VREG line via the transistor QD. Besides, the electric charges get confluent into the VREG line from all the APD circuits. Normally, an output impedance of a constant potential generating circuit is not 0, and hence, when a large current flows into the output thereof, the constant potential VREG is to rise. As a result, a discharge capability of the discharge NPN bipolar transistor QD declines, and it follows that the fall propagation delay time increases. A degree of increase in this fall propagation delay time depends on the number of APD circuits which are simultaneously switched. Consequently, there is caused a defect of being inconvenient in actual use.
To obviate this defect, an ECL circuit which follows is constructed.
FIG. 16 is a circuit diagram showing a construction of a third prior art ECL circuit as disclosed in FIG. 5 in Japanese Patent Laid-Open Publication No.7-142991.
FIG. 16 shows the third ECL circuit that is substantially the same construction as the second ECL circuit in FIG. 14. The third ECL circuit is, however, constructed not by connecting the constant potential generating circuit directly to the emitter of the discharge NPN bipolar transistor QD but by connecting the emitter of the transistor QD to the supply reference potential VEE trough a capacitor CD and a constant current source ICO, which are connected in parallel.
According to this construction, the constant potential VREG is automatically set to such a potential that the current flowing through a route of GND-QU-QD-VREG, becomes the constant current ICO. A large load discharge current needed for transient switching is supplied through the capacitor CD.
In this circuit construction, however, the electric charges accumulated in the load capacitance must be temporarily stored in the capacitor CD, and it is therefore required that at least a capacitance over the load capacitance be secured for the capacitor CD. It may happen that this load capacitance ranges to several pF, and consequently there must be a defect of requiring a a comparatively large area for disposing the capacitor CD.
Further, the following defect arises. In the ECL circuit (Japanese Patent Laid-Open Publication No.7-58617) in which the reference potential VREG in the second ECL circuit shown in FIG. 14 serves as the supply reference potential VEE, since a VREG terminal in FIG. 14 is connected to a power supply for supplying the supply reference potential VEE, the supply reference potential VEE can be set to merely a value as small as -2 V, nevertheless, the supply reference potential VEE normally used is on the order of -4.5 V or -5.2 V.